458 lines
12 KiB
C
458 lines
12 KiB
C
/* devices.c
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*
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* Copyright (C) 2006-2023 wolfSSL Inc.
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*
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* This file is part of wolfSSL.
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*
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* wolfSSL is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfSSL is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* Minimalist BSP for IoT-Safe example based on
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* ST P-L596G-CELL02 + Quectel BG96 modem
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "devices.h"
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#define RTSCTS 0
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#define AUTOBR 0
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#define NVIC_UART1_IRQN (37)
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#define NVIC_UART2_IRQN (38)
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static char modem_rx_buf[256];
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static uint32_t modem_rx_idx = 0;
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static uint32_t modem_parser_idx = 0;
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static void usart1_init(void)
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{
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uint32_t reg;
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/* Enable PWR */
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RCC_APB1_ENR |= PWR_APB1_CLOCK_ER_VAL;
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/* Enable GPIOG */
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RCC_AHB2_ENR |= GPIOG_AHB2_CLOCK_ER_VAL;
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/* Enable VDDIO2 */
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while ((PWR_CR2 & PWR_CR2_IOSV) == 0) {
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PWR_CR2 |= PWR_CR2_IOSV;
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printf("Turning on VDDIO2\n");
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sleep_ms(1000);
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}
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/* Enable GPIOB */
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RCC_AHB2_ENR |= GPIOB_AHB2_CLOCK_ER_VAL;
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/* Set mode = AF */
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reg = GPIO_MODE(GPIOG_BASE) & ~(0x03 << (USART1_PIN_RX * 2));
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GPIO_MODE(GPIOG_BASE) = reg | (0x02 << (USART1_PIN_RX * 2));
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reg = GPIO_MODE(GPIOB_BASE) & ~(0x03 << (USART1_PIN_TX * 2));
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GPIO_MODE(GPIOB_BASE) = reg | (0x02 << (USART1_PIN_TX * 2));
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reg = GPIO_PUPD(GPIOG_BASE) & (0x03 << (USART1_PIN_RX * 2));
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reg = GPIO_PUPD(GPIOB_BASE) & (0x03 << (USART1_PIN_TX * 2));
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GPIO_PUPD(GPIOB_BASE) = reg | (0x01 << (USART1_PIN_TX * 2));
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#if RTSCTS
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reg = GPIO_MODE(GPIOG_BASE) & ~(0x03 << (USART1_PIN_RTS * 2));
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GPIO_MODE(GPIOG_BASE) = reg | (0x02 << (USART1_PIN_RTS * 2));
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GPIO_PUPD(GPIOG_BASE) &= (0x03 << (USART1_PIN_RTS * 2));
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reg = GPIO_MODE(GPIOG_BASE) & ~(0x03 << (USART1_PIN_CTS * 2));
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GPIO_MODE(GPIOG_BASE) = reg | (0x02 << (USART1_PIN_CTS * 2));
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GPIO_PUPD(GPIOG_BASE) &= (0x03 << (USART1_PIN_CTS * 2));
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#endif
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/* Set alternate functions */
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reg = GPIO_AFH(GPIOG_BASE) & ~(0xf << ((USART1_PIN_RX - 8) * 4));
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GPIO_AFH(GPIOG_BASE) = reg | (7 << ((USART1_PIN_RX - 8) * 4));
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reg = GPIO_AFL(GPIOB_BASE) & ~(0xf << ((USART1_PIN_TX) * 4));
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GPIO_AFL(GPIOB_BASE) = reg | (7 << ((USART1_PIN_TX) * 4));
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#if RTSCTS
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/* RTS/CTS alt fn */
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reg = GPIO_AFH(GPIOG_BASE) & ~(0xf << ((USART1_PIN_RTS - 8) * 4));
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GPIO_AFH(GPIOG_BASE) = reg | (USART1_AF << ((USART1_PIN_RTS - 8) * 4));
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reg = GPIO_AFH(GPIOG_BASE) & ~(0xf << ((USART1_PIN_CTS - 8) * 4));
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GPIO_AFH(GPIOG_BASE) = reg | (USART1_AF << ((USART1_PIN_CTS - 8) * 4));
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#endif
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/* Enable USART clock */
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RCC_APB2_ENR |= USART1_APB2_CLOCK_ER_VAL;
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}
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static void usart2_init(void)
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{
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uint32_t reg;
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RCC_AHB2_ENR |= GPIOD_AHB2_CLOCK_ER_VAL | GPIOA_AHB2_CLOCK_ER_VAL;
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/* Set mode = AF */
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reg = GPIO_MODE(GPIOD_BASE) & ~(0x03 << (USART2_PIN_RX * 2));
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GPIO_MODE(GPIOD_BASE) = reg | (0x02 << (USART2_PIN_RX * 2));
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reg = GPIO_MODE(GPIOA_BASE) & ~(0x03 << (USART2_PIN_TX * 2));
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GPIO_MODE(GPIOA_BASE) = reg | (0x02 << (USART2_PIN_TX * 2));
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/* Set alternate functions */
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reg = GPIO_AFL(GPIOD_BASE) & ~(0xf << ((USART2_PIN_RX) * 4));
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GPIO_AFL(GPIOD_BASE) = reg | (7 << ((USART2_PIN_RX) * 4));
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reg = GPIO_AFL(GPIOA_BASE) & ~(0xf << ((USART2_PIN_TX) * 4));
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GPIO_AFL(GPIOA_BASE) = reg | (7 << ((USART2_PIN_TX) * 4));
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/* Enable USART clock */
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RCC_APB1_ENR |= USART2_APB1_CLOCK_ER_VAL;
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}
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int usart_tx(uint32_t dev, const uint8_t c)
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{
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volatile uint32_t reg;
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do {
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reg = USART_ISR(dev);
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} while ((reg & USART_ISR_TXE) == 0);
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USART_TDR(dev) = c;
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return 1;
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}
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int usart_rx(uint32_t dev, uint8_t *c)
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{
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int ret = 0;
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if (dev == USART1_BASE) {
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if (modem_rx_idx > modem_parser_idx) {
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*c = (uint8_t)(modem_rx_buf[modem_parser_idx++]);
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if (modem_rx_idx == modem_parser_idx) {
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modem_rx_idx = 0;
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modem_parser_idx = 0;
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}
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ret = 1;
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}
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} else {
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volatile uint32_t reg = USART_ISR(dev);
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if ((reg & USART_ISR_RXNE) != 0) {
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reg = USART_RDR(dev);
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*c = (uint8_t)(reg & 0xff);
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ret = 1;
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}
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}
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return ret;
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}
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int usart_init(uint32_t dev, uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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int rtscts = 0;
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if (dev == USART1_BASE) {
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usart1_init();
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#if RTSCTS
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rtscts = 1;
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#endif
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}
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else if (dev == USART2_BASE)
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usart2_init();
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else
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return -1;
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/* Turn off the device */
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USART_CR1(dev) &= ~(USART_CR1_ENABLE);
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/* Configure for TX + RX */
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USART_CR1(dev) |= (USART_CR1_TX_ENABLE | USART_CR1_RX_ENABLE);
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/* Configure clock */
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USART_BRR(dev) = CLOCK_SPEED / (bitrate);
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/* Configure data bits */
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if (data == 8)
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USART_CR1(dev) &= ~USART_CR1_SYMBOL_LEN;
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else
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USART_CR1(dev) |= USART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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USART_CR1(dev) |= USART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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/* FALL THROUGH */
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case 'E':
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USART_CR1(dev) |= USART_CR1_PARITY_ENABLED;
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break;
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default:
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USART_CR1(dev) &= ~(USART_CR1_PARITY_ENABLED | USART_CR1_PARITY_ODD);
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}
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/* Set stop bits (not supported) */
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(void)stop;
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/* Set rtscts */
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if (rtscts)
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USART_CR3(dev) |= USART_CR3_CTSE | USART_CR3_RTSE;
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#if AUTOBR
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/* Enable ABR */
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USART_CR2(dev) |= USART_CR2_ABREN;
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#endif
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if (dev == USART1_BASE) {
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USART_CR1(dev) |= USART_CR1_RXNEIE | USART_CR1_PEIE;
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USART_CR3(dev) |= USART_CR3_EIE;
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nvic_irq_enable(NVIC_UART1_IRQN);
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nvic_irq_setprio(NVIC_UART1_IRQN, 0);
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}
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/* Turn on uart */
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USART_CR1(dev) |= USART_CR1_ENABLE;
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return 0;
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}
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/* STDOUT on USART2 */
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int _write(void *r, uint8_t *text, int len)
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{
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char *p = (char *)text;
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(void)r;
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while(*p && (p < (char *)(text + len))) {
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usart_tx(USART2_BASE, *p);
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p++;
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}
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return len;
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}
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/* newlib backend calls */
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extern unsigned int _start_heap;
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void * _sbrk(unsigned int incr)
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{
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static unsigned char *heap = NULL;
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void *old_heap = heap;
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if (((incr >> 2) << 2) != incr)
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incr = ((incr >> 2) + 1) << 2;
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if (old_heap == NULL)
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old_heap = heap = (unsigned char *)&_start_heap;
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heap += incr;
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return old_heap;
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}
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void * _sbrk_r(unsigned int incr)
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{
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static unsigned char *heap = NULL;
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void *old_heap = heap;
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if (((incr >> 2) << 2) != incr)
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incr = ((incr >> 2) + 1) << 2;
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if (old_heap == NULL)
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old_heap = heap = (unsigned char *)&_start_heap;
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heap += incr;
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return old_heap;
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}
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int _close(int fd)
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{
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return -1;
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}
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int _fstat(int fd)
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{
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return -1;
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}
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int _lseek(int fd, int whence, int off)
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{
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return -1;
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}
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int _read(uint8_t *buf, int len)
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{
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return -1;
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}
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int _isatty(int fd)
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{
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return 1;
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}
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/* Clock + waitstates settings */
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static void flash_set_waitstates(unsigned int waitstates)
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{
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uint32_t reg = FLASH_ACR;
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if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates)
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FLASH_ACR |= ((reg & ~FLASH_ACR_LATENCY_MASK) | waitstates);
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}
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void clock_pll_on(void)
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{
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uint32_t reg32;
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uint32_t cpu_freq;
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uint32_t hpre, ppre1, ppre2;
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uint32_t flash_waitstates;
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/* Select clock parameters (CPU Speed = 80MHz) */
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cpu_freq = 80000000;
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flash_waitstates = 4;
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flash_set_waitstates(flash_waitstates);
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/* Configure + enable internal high-speed oscillator. */
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RCC_CR = (RCC_CR & (~RCC_CR_MSIRANGE_Msk)) | RCC_CR_MSIRANGE_6;
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RCC_CR |= RCC_CR_MSIRGSEL;
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RCC_CR |= RCC_CR_MSION;
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DMB();
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while ((RCC_CR & RCC_CR_MSIRDY) == 0)
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;
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/* Select MSI as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_SW_MASK);
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RCC_CFGR = (reg32 | RCC_CFGR_SW_MSI);
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DMB();
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/*
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* Set prescalers
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*/
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hpre = RCC_PRESCALER_DIV_NONE;
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ppre1 = RCC_PRESCALER_DIV_NONE;
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ppre2 = RCC_PRESCALER_DIV_NONE;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (hpre & RCC_CFGR_HPRE_MASK) << RCC_CFGR_HPRE_SHIFT;
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DMB();
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
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DMB();
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reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
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DMB();
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/* Set PLLCFGR parameter */
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RCC_PLLCFGR = PLLCFGR_PLLM | PLLCFGR_PLLN |
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PLLCFGR_PLLP | PLLCFGR_PLLQ |
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PLLCFGR_PLLR | RCC_PLLCFGR_PLLP_EN |
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RCC_PLLCFGR_PLLQ_EN | RCC_PLLCFGR_PLLR_EN |
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RCC_PLLCFGR_PLLSRC_MSI;
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/* Enable PLL oscillator and wait for it to stabilize. */
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RCC_CR |= RCC_CR_PLLON;
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DMB();
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while ((RCC_CR & RCC_CR_PLLRDY) == 0)
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;
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/* Select PLL as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_SW_MASK);
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RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
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DMB();
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/* Wait for PLL clock to be selected (via SWS, bits 3:2) */
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while (((RCC_CFGR >> 2) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL)
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;
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RCC_CCIPR |= (1 << 26);
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PWR_CR1 |= PWR_CR1_DBP;
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}
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/* Modem via STMod+ connector */
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static int stmod_en_init = 0;
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static void stmod_pin_init(void)
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{
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uint32_t reg;
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RCC_AHB2_ENR |=
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GPIOA_AHB2_CLOCK_ER_VAL |
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GPIOB_AHB2_CLOCK_ER_VAL |
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GPIOC_AHB2_CLOCK_ER_VAL |
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GPIOD_AHB2_CLOCK_ER_VAL |
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GPIOI_AHB2_CLOCK_ER_VAL;
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/* 'enable' pin */
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reg = GPIO_MODE(STMOD_EN_PORT) & ~(0x03 << (STMOD_EN_PIN * 2));
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GPIO_MODE(STMOD_EN_PORT) = reg | (0x01 << (STMOD_EN_PIN * 2));
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/* RST pin */
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reg = GPIO_MODE(STMOD_MODEM_RST_PORT) & ~(0x03 << (STMOD_MODEM_RST_PIN * 2));
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GPIO_MODE(STMOD_MODEM_RST_PORT) = reg | (0x01 << (STMOD_MODEM_RST_PIN * 2));
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/* DTR pin */
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reg = GPIO_MODE(STMOD_MODEM_DTR_PORT) & ~(0x03 << (STMOD_MODEM_DTR_PIN * 2));
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GPIO_MODE(STMOD_MODEM_DTR_PORT) = reg | (0x01 << (STMOD_MODEM_DTR_PIN * 2));
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/* Sim select pins */
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reg = GPIO_MODE(STMOD_SIM_SELECT0_PORT) & ~(0x03 << (STMOD_SIM_SELECT0_PIN * 2));
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GPIO_MODE(STMOD_SIM_SELECT0_PORT) = reg | (0x01 << (STMOD_SIM_SELECT0_PIN * 2));
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reg = GPIO_MODE(STMOD_SIM_SELECT1_PORT) & ~(0x03 << (STMOD_SIM_SELECT1_PIN * 2));
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GPIO_MODE(STMOD_SIM_SELECT1_PORT) = reg | (0x01 << (STMOD_SIM_SELECT1_PIN * 2));
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}
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void stmod_modem_enable(void)
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{
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if (!stmod_en_init) {
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stmod_pin_init();
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stmod_en_init = 1;
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}
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/* initial pin state */
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gpio_set(STMOD_EN_PORT, STMOD_EN_PIN);
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gpio_set(STMOD_MODEM_RST_PORT, STMOD_MODEM_RST_PIN);
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gpio_set(STMOD_MODEM_DTR_PORT, STMOD_MODEM_DTR_PIN);
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sleep_ms(200);
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gpio_clear(STMOD_MODEM_RST_PORT, STMOD_MODEM_RST_PIN);
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gpio_clear(STMOD_EN_PORT, STMOD_EN_PIN);
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sleep_ms(2500);
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/* ON/OFF sequence to clear state */
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gpio_set(STMOD_EN_PORT, STMOD_EN_PIN);
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sleep_ms(700);
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gpio_clear(STMOD_EN_PORT, STMOD_EN_PIN);
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sleep_ms(1000);
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gpio_set(STMOD_EN_PORT, STMOD_EN_PIN);
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sleep_ms(50);
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gpio_clear(STMOD_EN_PORT, STMOD_EN_PIN);
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sleep_ms(30);
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gpio_set(STMOD_EN_PORT, STMOD_EN_PIN); /* Modem is on. */
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printf("Modem booting...\n");
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sleep_ms(5000);
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printf("Modem is on.\r\n");
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}
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void stmod_modem_disable(void)
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{
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if (!stmod_en_init) {
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stmod_pin_init();
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stmod_en_init = 1;
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}
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gpio_clear(STMOD_EN_PORT, STMOD_EN_PIN);
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}
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extern volatile unsigned jiffies;
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void systick_enable(void)
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{
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SYSTICK_RVR = ((CLOCK_SPEED / 1000) - 1);
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SYSTICK_CVR = 0;
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SYSTICK_CSR |= 0x07;
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}
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void sleep_ms(unsigned ms)
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{
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unsigned end = jiffies + ms;
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while(jiffies < end)
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__asm__ volatile("wfi");
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}
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void isr_usart1(void)
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{
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uint32_t reg;
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reg = USART_ISR(USART1_BASE);
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if (reg & USART_ISR_RXNE) {
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modem_rx_buf[modem_rx_idx++] = (char)USART_RDR(USART1_BASE);
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} else {
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USART_ICR(USART1_BASE) |= 2 | USART_ICR_CMCF; /* FECF + CMCF*/
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}
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}
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