211 lines
7.5 KiB
C
211 lines
7.5 KiB
C
/* armtarget.c
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*
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* Copyright (C) 2006-2023 wolfSSL Inc.
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*
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* This file is part of wolfSSL.
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*
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* wolfSSL is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfSSL is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <wolfssl/wolfcrypt/settings.h>
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#include <wolfssl/ssl.h>
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#include <wolfssl/wolfcrypt/random.h> /* for CUSTOM_RAND_TYPE */
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#include <stdint.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#ifdef USE_WOLF_ARM_STARTUP
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/* Memory initialization */
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extern uint32_t __data_load_start__[];
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extern uint32_t __data_start__[];
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extern uint32_t __data_end__[];
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extern uint32_t __bss_start__[];
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extern uint32_t __bss_end__[];
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extern uint32_t __stack_process_end__[];
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extern uint32_t __heap_start__[];
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extern uint32_t __heap_end__[];
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/* Copy memory: src=Source, dst_beg=Destination Begin, dst_end=Destination End */
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void memcpy32(uint32_t* src, uint32_t* dst_beg, uint32_t* dst_end)
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{
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while (dst_beg < dst_end) {
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*dst_beg++ = *src++;
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}
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}
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/* Zero address in range */
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void meminit32(uint32_t* start, uint32_t* end)
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{
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while (start < end) {
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*start++ = 0;
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}
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}
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#endif /* USE_WOLF_ARM_STARTUP */
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/* Entry Point */
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void reset_handler(void)
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{
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#ifdef USE_WOLF_ARM_STARTUP
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/* Init sections */
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memcpy32(__data_load_start__, __data_start__, __data_end__);
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meminit32(__bss_start__, __bss_end__);
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/* Init heap */
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__heap_start__[0] = 0;
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__heap_start__[1] = ((uintptr_t)__heap_end__ - (uintptr_t)__heap_start__);
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#endif /* USE_WOLF_ARM_STARTUP */
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/* Start main */
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extern int main(void);
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main();
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/* Application has ended, so busy wait */
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while(1);
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}
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#ifdef USE_WOLF_ARM_STARTUP
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// Vector Exception/Interrupt Handlers
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static void Default_Handler(void)
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{
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/* If we get here then need to implement real IRQ handler */
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while(1);
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}
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__attribute__((section(".sys"))) __attribute__ ((used))
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void HardFault_HandlerC( uint32_t *hardfault_args )
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{
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/* These are volatile to try and prevent the compiler/linker optimizing them
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away as the variables never actually get used. If the debugger won't show the
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values of the variables, make them global my moving their declaration outside
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of this function. */
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volatile uint32_t stacked_r0;
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volatile uint32_t stacked_r1;
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volatile uint32_t stacked_r2;
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volatile uint32_t stacked_r3;
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volatile uint32_t stacked_r12;
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volatile uint32_t stacked_lr;
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volatile uint32_t stacked_pc;
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volatile uint32_t stacked_psr;
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volatile uint32_t _CFSR;
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volatile uint32_t _HFSR;
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volatile uint32_t _DFSR;
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volatile uint32_t _AFSR;
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volatile uint32_t _BFAR;
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volatile uint32_t _MMAR;
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stacked_r0 = ((uint32_t)hardfault_args[0]);
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stacked_r1 = ((uint32_t)hardfault_args[1]);
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stacked_r2 = ((uint32_t)hardfault_args[2]);
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stacked_r3 = ((uint32_t)hardfault_args[3]);
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stacked_r12 = ((uint32_t)hardfault_args[4]);
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stacked_lr = ((uint32_t)hardfault_args[5]);
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stacked_pc = ((uint32_t)hardfault_args[6]);
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stacked_psr = ((uint32_t)hardfault_args[7]);
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// Configurable Fault Status Register
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// Consists of MMSR, BFSR and UFSR
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_CFSR = (*((volatile uint32_t *)(0xE000ED28)));
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// Hard Fault Status Register
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_HFSR = (*((volatile uint32_t *)(0xE000ED2C)));
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// Debug Fault Status Register
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_DFSR = (*((volatile uint32_t *)(0xE000ED30)));
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// Auxiliary Fault Status Register
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_AFSR = (*((volatile uint32_t *)(0xE000ED3C)));
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// Read the Fault Address Registers. These may not contain valid values.
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// Check BFARVALID/MMARVALID to see if they are valid values
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// MemManage Fault Address Register
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_MMAR = (*((volatile uint32_t *)(0xE000ED34)));
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// Bus Fault Address Register
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_BFAR = (*((volatile uint32_t *)(0xE000ED38)));
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printf ("\n\nHard fault handler (all numbers in hex):\n");
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printf ("R0 = %lx\n", stacked_r0);
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printf ("R1 = %lx\n", stacked_r1);
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printf ("R2 = %lx\n", stacked_r2);
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printf ("R3 = %lx\n", stacked_r3);
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printf ("R12 = %lx\n", stacked_r12);
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printf ("LR [R14] = %lx subroutine call return address\n", stacked_lr);
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printf ("PC [R15] = %lx program counter\n", stacked_pc);
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printf ("PSR = %lx\n", stacked_psr);
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printf ("CFSR = %lx\n", _CFSR);
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printf ("HFSR = %lx\n", _HFSR);
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printf ("DFSR = %lx\n", _DFSR);
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printf ("AFSR = %lx\n", _AFSR);
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printf ("MMAR = %lx\n", _MMAR);
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printf ("BFAR = %lx\n", _BFAR);
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// Break into the debugger
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__asm("BKPT #0\n");
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}
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__attribute__((section(".sys"))) __attribute__( ( naked ) )
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void HardFault_Handler(void)
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{
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__asm volatile
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(
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" movs r0,#4 \n" /* load bit mask into R0 */
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" mov r1, lr \n" /* load link register into R1 */
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" tst r0, r1 \n" /* compare with bitmask */
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" beq _MSP \n" /* if bitmask is set: stack pointer is in PSP. Otherwise in MSP */
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" mrs r0, psp \n" /* otherwise: stack pointer is in PSP */
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" b _GetPC \n" /* go to part which loads the PC */
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"_MSP: \n" /* stack pointer is in MSP register */
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" mrs r0, msp \n" /* load stack pointer into R0 */
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"_GetPC: \n" /* find out where the hard fault happened */
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" ldr r1,[r0,#20] \n" /* load program counter into R1. R1 contains address of the next instruction where the hard fault happened */
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" ldr r2, =HardFault_HandlerC \n"
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" bx r2 \n"
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" bx lr \n" /* decode more information. R0 contains pointer to stack frame */
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);
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}
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/* Vectors Table */
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typedef void (*vector_entry)(void);
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const vector_entry vectors[] __attribute__ ((section(".vectors"),used)) =
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{
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/* Interrupt Vector Table Function Pointers */
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// Address Vector IRQ Source module Source description
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(vector_entry)__stack_process_end__, // ARM core Initial Supervisor SP
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reset_handler, // 0x0000_0004 1 - ARM core Initial Program Counter
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Default_Handler, // 0x0000_0008 2 - ARM core Non-maskable Interrupt (NMI)
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HardFault_Handler, // 0x0000_000C 3 - ARM core Hard Fault
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Default_Handler, // 0x0000_0010 4 -
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HardFault_Handler, // 0x0000_0014 5 - ARM core Bus Fault
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HardFault_Handler, // 0x0000_0018 6 - ARM core Usage Fault
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Default_Handler, // 0x0000_001C 7 -
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Default_Handler, // 0x0000_0020 8 -
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Default_Handler, // 0x0000_0024 9 -
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Default_Handler, // 0x0000_0028 10 -
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Default_Handler, // 0x0000_002C 11 - ARM core Supervisor call (SVCall)
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Default_Handler, // 0x0000_0030 12 - ARM core Debug Monitor
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Default_Handler, // 0x0000_0034 13 -
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Default_Handler, // 0x0000_0038 14 - ARM core Pendable request for system service (PendableSrvReq)
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Default_Handler, // 0x0000_003C 15 - ARM core System tick timer (SysTick)
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/* remainder go below */
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};
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#endif /* USE_WOLF_ARM_STARTUP */
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