303 lines
9.6 KiB
C
303 lines
9.6 KiB
C
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/* devices.h
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*
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* Copyright (C) 2006-2023 wolfSSL Inc.
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*
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* This file is part of wolfSSL.
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*
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* wolfSSL is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfSSL is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* Minimalist BSP for IoT-Safe example based on
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* ST P-L596G-CELL02 + Quectel BG96 modem
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*/
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#ifndef STM32L496_DEVICES
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#define STM32L496_DEVICES
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/* CPU clock speed */
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//#define CLOCK_SPEED 14200000
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//#define CLOCK_SPEED 6000000
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#define CLOCK_SPEED 40000000
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/* Memory mapping */
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#define USART1_BASE (0x40013800UL)
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#define USART2_BASE (0x40004400UL)
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#define GPIOA_BASE (0x48000000UL)
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#define GPIOB_BASE (0x48000400UL)
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#define GPIOC_BASE (0x48000800UL)
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#define GPIOD_BASE (0x48000C00UL)
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#define GPIOE_BASE (0x48001000UL)
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#define GPIOF_BASE (0x48001400UL)
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#define GPIOG_BASE (0x48001800UL)
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#define GPIOH_BASE (0x48001C00UL)
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#define GPIOI_BASE (0x48002000UL)
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#define RCC_BASE (0x40021000UL)
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#define PWR_BASE (0x40007000UL)
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/* USART */
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#define USART_CR1(x) (*((volatile uint32_t *)(x + 0x00)))
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#define USART_CR2(x) (*((volatile uint32_t *)(x + 0x04)))
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#define USART_CR3(x) (*((volatile uint32_t *)(x + 0x08)))
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#define USART_BRR(x) (*((volatile uint32_t *)(x + 0x0C)))
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#define USART_ISR(x) (*((volatile uint32_t *)(x + 0x1C)))
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#define USART_ICR(x) (*((volatile uint32_t *)(x + 0x20)))
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#define USART_RDR(x) (*((volatile uint8_t *)(x + 0x24)))
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#define USART_TDR(x) (*((volatile uint8_t *)(x + 0x28)))
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/* GPIO */
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#define GPIO_MODE(x) (*((volatile uint32_t *)(x + 0x00)))
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#define GPIO_SPEED(x) (*((volatile uint32_t *)(x + 0x08)))
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#define GPIO_PUPD(x) (*((volatile uint32_t *)(x + 0x0C)))
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#define GPIO_AFL(x) (*((volatile uint32_t *)(x + 0x20)))
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#define GPIO_AFH(x) (*((volatile uint32_t *)(x + 0x24)))
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#define GPIO_BSSR(x) (*((volatile uint32_t *)(x + 0x18)))
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/* RCC */
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
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#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
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#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C))
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#define RCC_CCIPR (*(volatile uint32_t *)(RCC_BASE + 0x88))
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#define RCC_AHB1_ENR (*(volatile uint32_t *)(RCC_BASE + 0x48))
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#define RCC_AHB2_ENR (*(volatile uint32_t *)(RCC_BASE + 0x4C))
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#define RCC_AHB3_ENR (*(volatile uint32_t *)(RCC_BASE + 0x50))
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#define RCC_APB1_ENR (*(volatile uint32_t *)(RCC_BASE + 0x58))
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#define RCC_APB2_ENR (*(volatile uint32_t *)(RCC_BASE + 0x60))
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/* PWR */
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#define PWR_CR1 (*(volatile uint32_t *)(PWR_BASE + 0x00))
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#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
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#define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x014))
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#define PWR_CR1_DBP (1 << 8)
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#define PWR_CR2_PVME2 (1 << 5)
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#define PWR_CR2_IOSV (1 << 9)
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#define PWR_SR2_PVMO2 (1 << 13)
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/* FLASH registers + latency mask */
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#define FLASH_BASE 0x40022000
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
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#define FLASH_ACR_LATENCY_MASK (0x03)
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/* RCC: Periph enable flags */
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#define USART1_APB2_CLOCK_ER_VAL (1 << 14)
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#define USART2_APB1_CLOCK_ER_VAL (1 << 17)
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#define PWR_APB1_CLOCK_ER_VAL (1 << 28)
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#define GPIOA_AHB2_CLOCK_ER_VAL (1 << 0)
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#define GPIOB_AHB2_CLOCK_ER_VAL (1 << 1)
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#define GPIOC_AHB2_CLOCK_ER_VAL (1 << 2)
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#define GPIOD_AHB2_CLOCK_ER_VAL (1 << 3)
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#define GPIOE_AHB2_CLOCK_ER_VAL (1 << 4)
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#define GPIOF_AHB2_CLOCK_ER_VAL (1 << 5)
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#define GPIOG_AHB2_CLOCK_ER_VAL (1 << 6)
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#define GPIOH_AHB2_CLOCK_ER_VAL (1 << 7)
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#define GPIOI_AHB2_CLOCK_ER_VAL (1 << 8)
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/* Pinout: USART */
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#define USART1_PIN_RX (10) /* PG10 */
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#define USART1_PIN_TX (6) /* PB6 */
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#define USART1_PIN_CTS (11) /* PG11 */
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#define USART1_PIN_RTS (12) /* PG12 */
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#define USART1_AF (7)
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#define USART2_PIN_RX (6) /* PD6 */
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#define USART2_PIN_TX (2) /* PA2 */
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#define USART2_AF (7)
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/* USART registers: flags */
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#define USART_CR1_ENABLE (1 << 0)
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#define USART_CR1_TX_ENABLE (1 << 3)
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#define USART_CR1_RX_ENABLE (1 << 2)
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#define USART_CR1_RXNEIE (1 << 5)
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#define USART_CR1_PEIE (1 << 8)
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#define USART_CR1_PARITY_ODD (1 << 9)
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#define USART_CR1_PARITY_ENABLED (1 << 10)
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#define USART_CR1_SYMBOL_LEN (1 << 28)
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#define USART_CR2_ABREN (1 << 20)
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#define USART_CR3_EIE (1 << 0)
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#define USART_CR3_RTSE (1 << 8)
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#define USART_CR3_CTSE (1 << 9)
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#define USART_ISR_TXE (1 << 7)
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#define USART_ISR_RXNE (1 << 5)
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#define USART_ICR_CTSCF (1 << 9)
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#define USART_ICR_CMCF (1 << 17)
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/* RCC_CR/CFGR/PLLCFGR values */
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#define RCC_PRESCALER_DIV_NONE 0
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#define RCC_PRESCALER_DIV_2 8
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#define RCC_PRESCALER_DIV_4 9
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_MSIRGSEL (1 << 3)
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#define RCC_CR_MSIRDY (1 << 1)
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#define RCC_CR_MSION (1 << 0)
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#define RCC_CR_HSIRDY (1 << 10)
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#define RCC_CR_HSION (1 << 8)
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#define RCC_CR_MSIRANGE_SHIFT 4
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#define RCC_CR_MSIRANGE_9 (0x09 << 4)
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#define RCC_CR_MSIRANGE_6 (0x06 << 4)
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#define RCC_CR_MSIRANGE_Msk (0x0F << 4)
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#define RCC_CFGR_HPRE_MASK 0x0F
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#define RCC_CFGR_PPRE1_MASK 0x07
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#define RCC_CFGR_PPRE2_MASK 0x07
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#define RCC_CFGR_HPRE_SHIFT 4
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#define RCC_CFGR_PPRE1_SHIFT 8
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#define RCC_CFGR_PPRE2_SHIFT 11
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#define RCC_CFGR_SW_MSI 0x0
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#define RCC_CFGR_SW_PLL 0x3
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#define RCC_CFGR_SW_MASK 0x3
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/* Bits 0:1 SRC */
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#define RCC_PLLCFGR_SRC_SHIFT 0
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#define RCC_PLLCFGR_PLLSRC_MSI 0x1
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#define RCC_PLLCFGR_PLLSRC_MASK 0x3
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/* Bits 4:6 PLLM */
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//#define PLLCFGR_PLLM (0x4 << 4)
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#define PLLCFGR_PLLM (0x1 << 4)
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#define RCC_PLLCFGR_PLLM_MASK (0x7 << 4)
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/* Bits 8:14 PLLN */
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//#define PLLCFGR_PLLN (71 << 8)
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#define PLLCFGR_PLLN (40 << 8)
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#define RCC_PLLCFGR_PLLN_MASK (0x7f << 8)
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/* Bits 27:31 PLLPDIV */
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#define PLLCFGR_PLLP (2 << 27)
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#define RCC_PLLCFGR_PLLP_MASK (0x1F << 27)
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/* Bits 21:22 PLLQ */
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#define PLLCFGR_PLLQ (0 << 21)
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#define RCC_PLLCFGR_PLLQ_MASK (0x3 << 21)
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/* Bits 25:26 PLLR */
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//#define PLLCFGR_PLLR (2 << 25)
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#define PLLCFGR_PLLR (0 << 25)
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#define RCC_PLLCFGR_PLLR_MASK (0x3 << 25)
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/* Enablers */
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#define RCC_PLLCFGR_PLLP_EN (0 << 16)
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#define RCC_PLLCFGR_PLLQ_EN (0 << 20)
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#define RCC_PLLCFGR_PLLR_EN (1 << 24)
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/* Systick */
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#define SYSTICK_BASE (0xE000E010)
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#define SYSTICK_CSR (*(volatile uint32_t *)(SYSTICK_BASE + 0x00))
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#define SYSTICK_RVR (*(volatile uint32_t *)(SYSTICK_BASE + 0x04))
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#define SYSTICK_CVR (*(volatile uint32_t *)(SYSTICK_BASE + 0x08))
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#define SYSTICK_CALIB (*(volatile uint32_t *)(SYSTICK_BASE + 0x0C))
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/* STMod+ connector pinout
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*
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* Connector STM32L4
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* pins pins
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*
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* 1 11 PG11 PH2
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* 2 12 PB6 PB2
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* 3 13 PG10 PA4
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* 4 14 PG12 PA0
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* 5 15 GND 5V
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* 6 16 5V GND
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* 7 17 PB8 PC7
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* 8 18 PI3 PC2
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* 9 19 PD3 PB12
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* 10 20 PB7 PC2
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*
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*/
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#define STMOD_EN_PORT GPIOD_BASE
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#define STMOD_EN_PIN 3
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#define STMOD_SIM_SELECT0_PORT GPIOC_BASE
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#define STMOD_SIM_SELECT0_PIN 2
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#define STMOD_SIM_SELECT1_PORT GPIOI_BASE
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#define STMOD_SIM_SELECT1_PIN 3
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#define STMOD_MODEM_RST_PORT GPIOB_BASE
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#define STMOD_MODEM_RST_PIN 2
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#define STMOD_MODEM_DTR_PORT GPIOA_BASE
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#define STMOD_MODEM_DTR_PIN 0
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void stmod_modem_enable(void);
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void stmod_modem_disable(void);
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/* inline functions for GPIO */
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static inline void gpio_set(uint32_t port, uint32_t pin)
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{
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GPIO_BSSR(port) |= (1 << pin);
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}
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static inline void gpio_clear(uint32_t port, uint32_t pin)
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{
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GPIO_BSSR(port) |= (1 << (16 + pin));
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}
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/* Exported functions (from devices.c) */
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void clock_pll_on(void);
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int usart_init(uint32_t dev, uint32_t bitrate, uint8_t data, char parity, uint8_t stop);
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int usart_tx(uint32_t dev, const uint8_t c);
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int usart_rx(uint32_t dev, uint8_t *c);
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void systick_enable(void);
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void sleep_ms(unsigned ms);
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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/* Nvic */
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#define NVIC_ISER_BASE (0xE000E100)
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#define NVIC_ICER_BASE (0xE000E180)
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#define NVIC_ICPR_BASE (0xE000E280)
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#define NVIC_IPRI_BASE (0xE000E400)
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static inline void nvic_irq_enable(uint8_t n)
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{
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int i = n / 32;
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volatile uint32_t *nvic_iser = ((volatile uint32_t *)(NVIC_ISER_BASE + 4 * i));
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*nvic_iser |= (1 << (n % 32));
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}
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static inline void nvic_irq_disable(uint8_t n)
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{
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int i = n / 32;
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volatile uint32_t *nvic_icer = ((volatile uint32_t *)(NVIC_ICER_BASE + 4 * i));
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*nvic_icer |= (1 << (n % 32));
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}
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static inline void nvic_irq_setprio(uint8_t n, uint8_t prio)
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{
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volatile uint8_t *nvic_ipri = ((volatile uint8_t *)(NVIC_IPRI_BASE + n));
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*nvic_ipri = prio;
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}
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static inline void nvic_irq_clear(uint8_t n)
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{
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int i = n / 32;
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volatile uint8_t *nvic_icpr = ((volatile uint8_t *)(NVIC_ICPR_BASE + 4 * i));
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*nvic_icpr = (1 << (n % 32));
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}
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#endif /* guard */
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