346 lines
11 KiB
C
346 lines
11 KiB
C
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/* kinetis_hw.c
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*
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* Copyright (C) 2006-2023 wolfSSL Inc.
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*
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* This file is part of wolfSSL.
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*
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* wolfSSL is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfSSL is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include "hw.h"
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#include "user_settings.h"
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#if defined(FREESCALE) && defined(K_SERIES)
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/**********************************************
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* NOTE: Customize for actual hardware
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**********************************************/
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// CPU include for Rowley CrossWorks packages
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// $(TargetsDir) location:
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// On Mac OS/X: Users/USERNAME/Library/Rowley Associates Limited/CrossWorks for ARM/packages/targets/
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// On Windows: C:/Users/USERNAME/Application Data/Local/Rowley Associates Limited/CrossWorks for ARM/packages/targets/
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// On Linux: home/USERNAME/.rowley_associates_limited/CrossWorks for ARM/v4/packages/targets/
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// Located in $(TargetsDir)/Kinetis/CMSIS/
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#ifdef FREESCALE_KSDK_BM
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#include "fsl_common.h"
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#include "fsl_debug_console.h"
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#include "fsl_rtc.h"
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#include "fsl_trng.h"
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#include "fsl_lpuart.h"
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#include "fsl_port.h"
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#include "clock_config.h"
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#else
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#include <MK64F12.h> // Located in $(TargetsDir)/Kinetis/CMSIS/
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#endif
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// System clock
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#ifdef FREESCALE_KSDK_BM
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#define SYS_CLK_HZ SystemCoreClock
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#else
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#define SYS_CLK_HZ 96000000ul /* Core system clock in Hz */
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#define SYS_CLK_DRS MCG_C4_DRST_DRS(0x03) /* DRS 0=24MHz, 1=48MHz, 2=72MHz, 3=96MHz */
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#define SYS_CLK_DMX MCG_C4_DMX32_MASK /* 0=Disable DMX32 (lower actual speed), MCG_C4_DMX32_MASK=Enable DMX32 */
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#define SYS_CLK_DIV 1 /* System clock divisor */
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#define BUS_CLK_DIV 2 /* Bus clock divisor */
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#define BUS_CLK_KHZ (SYS_CLK_HZ/BUS_CLK_DIV) /* Helper to calculate bus speed for UART */
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#define FLASH_CLK_DIV 4 /* Flash clock divisor */
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#endif
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// UART TX Port, Pin, Mux and Baud
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#ifdef FREESCALE_KSDK_BM
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#define UART_PORT LPUART4 /* UART Port */
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#define UART_TX_PORT PORTC /* UART TX Port */
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#define UART_TX_PIN 15U /* UART TX Pin */
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#define UART_TX_MUX kPORT_MuxAlt3 /* Kinetis UART pin mux */
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#elif defined (WOLFSSL_FRDM_K64)
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#define UART_PORT UART0 /* UART Port */
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#define UART_TX_PORT PORTB /* UART TX Port */
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#define UART_TX_PIN 17U /* UART TX Pin */
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#define UART_TX_MUX 0x3 /* Kinetis UART pin mux */
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#else
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#define UART_PORT UART4 /* UART Port */
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#define UART_TX_PORT PORTE /* UART TX Port */
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#define UART_TX_PIN 24U /* UART TX Pin */
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#define UART_TX_MUX 0x3 /* Kinetis UART pin mux */
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#endif
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#define UART_BAUD_RATE 115200 /* UART Baud Rate */
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#ifdef WOLFSSL_FRDM_K64
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#define UART_BAUD UART_BAUD_RATE*8
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#else
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#define UART_BAUD UART_BAUD_RATE
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#endif
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/* Note: You will also need to update the UART clock gate in hw_uart_init (SIM_SCGC1_UART5_MASK) */
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/* Note: TWR-K60 is UART3, PTC17 */
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/* Note: FRDM-K64 is UART4, PTE24 or UART0 PTB17 for OpenOCD (SIM_SCGC4_UART0_MASK)*/
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/* Note: TWR-K64 is UART5, PTE8 */
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/* Note: FRDM-K82F is LPUART4 PTC15 Alt3 (OpenOCD UART) */
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/***********************************************/
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// Private functions
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static uint32_t mDelayCyclesPerUs = 0;
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#define NOP_FOR_LOOP_INSTRUCTION_COUNT 6
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static void delay_nop(uint32_t count)
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{
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int i;
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for(i=0; i<count; i++) {
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__asm volatile("nop");
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}
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}
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static void hw_mcg_init(void)
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{
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#ifdef FREESCALE_KSDK_BM
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BOARD_BootClockHSRUN();
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#else
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/* Adjust clock dividers (core/system=div/1, bus=div/2, flex bus=div/2, flash=div/4) */
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(SYS_CLK_DIV-1) | SIM_CLKDIV1_OUTDIV2(BUS_CLK_DIV-1) |
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SIM_CLKDIV1_OUTDIV3(BUS_CLK_DIV-1) | SIM_CLKDIV1_OUTDIV4(FLASH_CLK_DIV-1);
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/* Configure FEI internal clock speed */
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MCG->C4 = (SYS_CLK_DMX | SYS_CLK_DRS);
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while((MCG->C4 & (MCG_C4_DRST_DRS_MASK | MCG_C4_DMX32_MASK)) != (SYS_CLK_DMX | SYS_CLK_DRS));
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#endif
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}
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static void hw_gpio_init(void)
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{
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#ifdef FREESCALE_KSDK_BM
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CLOCK_EnableClock(kCLOCK_PortA);
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CLOCK_EnableClock(kCLOCK_PortB);
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CLOCK_EnableClock(kCLOCK_PortC);
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CLOCK_EnableClock(kCLOCK_PortD);
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CLOCK_EnableClock(kCLOCK_PortE);
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#else
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/* Enable clocks to all GPIO ports */
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SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK
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#ifdef SIM_SCGC5_PORTC_MASK
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| SIM_SCGC5_PORTC_MASK
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#endif
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#ifdef SIM_SCGC5_PORTD_MASK
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| SIM_SCGC5_PORTD_MASK
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#endif
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#ifdef SIM_SCGC5_PORTE_MASK
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| SIM_SCGC5_PORTE_MASK
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#endif
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);
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#if 0 /* Debug clock */
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/* ClockOut on PTC3 */
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PORTC->PCR[3] = PORT_PCR_MUX(0x05); /* Alt 5 */
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SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(0); /* FlexBus CLKOUT */
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#endif
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#endif
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}
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static void hw_uart_init(void)
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{
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#ifdef FREESCALE_KSDK_BM
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PORT_SetPinMux(UART_TX_PORT, UART_TX_PIN, UART_TX_MUX);
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CLOCK_SetLpuartClock(1); /* MCGPLLCLK */
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DbgConsole_Init((uint32_t)UART_PORT, UART_BAUD, DEBUG_CONSOLE_DEVICE_TYPE_LPUART, SYS_CLK_HZ);
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#else
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register uint16_t sbr, brfa;
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uint8_t temp;
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#ifdef WOLFSSL_FRDM_K64
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/* Enable UART core clock ONLY for FRDM-K64F */
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SIM->SCGC4 |= SIM_SCGC4_UART0_MASK;
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#else
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/* Enable UART core clock */
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/* Note: Remember to update me if UART_PORT changes */
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SIM->SCGC1 |= SIM_SCGC1_UART4_MASK;
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#endif
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/* Configure UART TX pin */
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UART_TX_PORT->PCR[UART_TX_PIN] = PORT_PCR_MUX(UART_TX_MUX);
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/* Disable transmitter and receiver while we change settings. */
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UART_PORT->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
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/* Configure the UART for 8-bit mode, no parity */
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UART_PORT->C1 = 0;
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/* Calculate baud settings */
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sbr = (uint16_t)((BUS_CLK_KHZ * 1000)/(UART_BAUD * 16));
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temp = UART_PORT->BDH & ~(UART_BDH_SBR(0x1F));
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UART_PORT->BDH = temp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));
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UART_PORT->BDL = (uint8_t)(sbr & UART_BDL_SBR_MASK);
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/* Determine if a fractional divider is needed to get closer to the baud rate */
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brfa = (((BUS_CLK_KHZ * 32000)/(UART_BAUD * 16)) - (sbr * 32));
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temp = UART_PORT->C4 & ~(UART_C4_BRFA(0x1F));
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UART_PORT->C4 = temp | UART_C4_BRFA(brfa);
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/* Enable receiver and transmitter */
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UART_PORT->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK);
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#endif
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}
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static void hw_rtc_init(void)
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{
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/* Init nop delay */
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mDelayCyclesPerUs = (SYS_CLK_HZ / 1000000 / NOP_FOR_LOOP_INSTRUCTION_COUNT);
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/* Enable RTC clock and oscillator */
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SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
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if (RTC->SR & RTC_SR_TIF_MASK) {
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/* Resets the RTC registers except for the SWR bit */
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RTC->CR |= RTC_CR_SWR_MASK;
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RTC->CR &= ~RTC_CR_SWR_MASK;
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/* Set TSR register to 0x1 to avoid the TIF bit being set in the SR register */
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RTC->TSR = 1;
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}
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/* Disable RTC Interrupts */
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RTC->IER = 0;
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/* Enable OSC */
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if ((RTC->CR & RTC_CR_OSCE_MASK) == 0) {
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/* Turn on */
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RTC->CR |= RTC_CR_OSCE_MASK;
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/* Wait RTC startup delay 1000 us */
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delay_us(1000);
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}
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/* Enable counter */
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RTC->SR |= RTC_SR_TCE_MASK;
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}
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static void hw_rand_init(void)
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{
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#ifdef FREESCALE_KSDK_BM
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trng_config_t trngConfig;
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TRNG_GetDefaultConfig(&trngConfig);
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/* Set sample mode of the TRNG ring oscillator to Von Neumann, for better random data.*/
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trngConfig.sampleMode = kTRNG_SampleModeVonNeumann;
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/* Initialize TRNG */
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TRNG_Init(TRNG0, &trngConfig);
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#else
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/* Enable RNG clocks */
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SIM->SCGC6 |= SIM_SCGC6_RNGA_MASK;
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SIM->SCGC3 |= SIM_SCGC3_RNGA_MASK;
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/* Wake up RNG to normal mode (take out of sleep) */
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RNG->CR &= ~RNG_CR_SLP_MASK;
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/* Enable High Assurance mode (Enables notification of security violations via SR[SECV]) */
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RNG->CR |= RNG_CR_HA_MASK;
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/* Enable RNG generation to RANDOUT FIFO */
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RNG->CR |= RNG_CR_GO_MASK;
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#endif
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}
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/* Public Functions */
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void hw_init(void)
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{
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hw_mcg_init();
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hw_gpio_init();
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hw_uart_init();
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hw_rtc_init();
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hw_rand_init();
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}
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uint32_t hw_get_time_sec(void)
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{
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/* Return RTC seconds */
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return RTC->TSR;
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}
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uint32_t hw_get_time_msec(void)
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{
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/* RTC TPR precision register increments every 32.768 kHz clock cycle */
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/* Convert with rounding crystal count (32768 or (1 << 15)) to milliseconds */
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return ( ((uint32_t)RTC->TPR * 1000) + ((1 << 15) / 2) ) / (1 << 15);
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}
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void hw_uart_printchar(int c)
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{
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#ifdef FREESCALE_KSDK_BM
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LPUART_WriteBlocking(UART_PORT, (const uint8_t*)&c, 1); /* Send the character */
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#else
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while(!(UART_PORT->S1 & UART_S1_TDRE_MASK)); /* Wait until space is available in the FIFO */
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UART_PORT->D = (uint8_t)c; /* Send the character */
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#endif
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}
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uint32_t hw_rand(void)
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{
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uint32_t rng;
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#ifdef FREESCALE_KSDK_BM
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TRNG_GetRandomData(TRNG0, &rng, sizeof(rng));
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#else
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while((RNG->SR & RNG_SR_OREG_LVL(0xF)) == 0) {}; /* Wait until FIFO has a value available */
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rng = RNG->OR; /* Return next value in FIFO output register */
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#endif
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return rng;
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}
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void delay_us(uint32_t microseconds)
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{
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delay_nop(mDelayCyclesPerUs * microseconds);
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}
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// Watchdog
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void hw_watchdog_disable(void)
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{
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WDOG->UNLOCK = 0xC520;
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WDOG->UNLOCK = 0xD928;
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WDOG->STCTRLH = WDOG_STCTRLH_ALLOWUPDATE_MASK;
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}
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// Flash configuration
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#define FSEC_UNSECURE 2
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#define FSEC_SECURE 0
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#define FSEC_FSLACC_DENIED 2
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#define FSEC_FSLACC_GRANTED 3
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#define FSEC_KEY_ENABLED 2
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#define FSEC_KEY_DISABLED 3
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#define FSEC_MASS_ERASE_DISABLE 2
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#define FSEC_MASS_ERASE_ENABLE 3
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struct flash_conf {
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uint8_t backdoor_key[8]; /* Backdoor Comparison Key */
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uint8_t fprot[4]; /* Program flash protection bytes */
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uint8_t fsec; /* Flash security byte */
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uint8_t fopt; /* Flash nonvolatile option byte */
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uint8_t feprot; /* FlexNVM: EEPROM protection byte */
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uint8_t fdprot; /* FlexNVM: Data flash protection byte */
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};
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const struct flash_conf flash_conf __attribute__ ((section (".flashconf"),used)) =
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{
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.backdoor_key = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
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.fprot = { 0xFF, 0xFF, 0xFF, 0xFF },
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.fsec = NV_FSEC_SEC(FSEC_UNSECURE) | NV_FSEC_FSLACC(FSEC_FSLACC_GRANTED) |
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NV_FSEC_MEEN(FSEC_MASS_ERASE_ENABLE) | NV_FSEC_KEYEN(FSEC_KEY_DISABLED),
|
||
|
|
.fopt = 0xFF,
|
||
|
|
.feprot = 0xFF,
|
||
|
|
.fdprot = 0xFF
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* FREESCALE && K_SERIES */
|